Invited talk by Mr. Rajshekar, a senior research fellow at IIT Delhi on Providing Accountability in Heterogeneous Systems-on-Chip
Modern systems-on-chip (SoCs) contain components designed by different organizations. When such an SoC miscomputes or underperforms in the field, discerning the responsible component is a non-trivial task. Accurate discernment is of great importance, because it can be hugely damaging to the organization's credibility in the market if it is held responsible for a faulty design. A perfectly accountable SoC is one in which the component at fault is always unambiguously detected.
Rajshekar K is a Senior Research Fellow at the Indian Institute of Technology Delhi. He has submitted his PhD thesis at the same institute, under the guidance of Dr. Smruti R. Sarangi. His research interests include computer architecture, hardware reliability, hardware security, accountability issues in heterogeneous 3PIP-containing SOCs, and microarchitectural simulation. He has published in leading journals such as ACM Transactions on Architecture and Code Optimization (TACO), and conferences such as Design, Automation and Test in Europe (DATE). He is one of chief designers, developers and maintainers of the popular open source architectural simulator Tejas. It is used in many universities, in India and across the globe, for both teaching and research purposes.