WriteSmoothing: Improving lifetime of non-volatile caches using intra-set wear-leveling

Conference/Journal
ACM
Authors
Sparsh Mittal Jeffrey S Vetter Dong Li
BibTex
Abstract
Abstract Driven by the trends of increasing core-count and bandwidth-wall problem, the size of last level caches (LLCs) has greatly increased. Since SRAM consumes high leakage power, researchers have explored use of non-volatile memories (NVMs) for designing caches as they provide high density and consume low leakage power. However, since NVMs have low write-endurance and the existing cache management policies are write variation-unaware, effective wear-leveling techniques are required for achieving ...