A Survey Of Architectural Approaches for Managing Embedded DRAM and Non-volatile On-chip Caches

Conference/Journal
IEEE
Authors
Sparsh Mittal Jeffrey S Vetter Dong Li
BibTex
Abstract
Abstract: Recent trends of CMOS scaling and increasing number of on-chip cores have led to a large increase in the size of on-chip caches. Since SRAM has low density and consumes large amount of leakage power, its use in designing on-chip caches has become more challenging. To address this issue, researchers are exploring the use of several emerging memory technologies, such as embedded DRAM, spin transfer torque RAM, resistive RAM, phase change RAM and domain wall memory. In this paper, we survey the ...