Using cache-coloring to mitigate inter-set write variation in non-volatile caches

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Abstract: In recent years, researchers have explored use of non-volatile devices such as STT- RAM (spin torque transfer RAM) for designing on-chip caches, since they provide high density and consume low leakage power. A common limitation of all non-volatile devices is their limited write endurance. Further, since existing cache management policies are write- variation unaware, excessive writes to a few blocks may lead to a quick failure of the whole cache. We propose an architectural technique for wear-leveling of non-volatile last level ...