A Technique for Write-endurance aware Management of Resistive RAM Last Level Caches

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Abstract Due to increasing cache sizes and large leakage consumption of SRAM device, conventional SRAM caches contribute significantly to the processor power consumption. Recently researchers have used non-volatile memory devices to design caches, since they provide high density, comparable read latency and low leakage power dissipation. However, their high write latency may increase the execution time and hence, leakage energy consumption. Also, since their write endurance is small, a conventional energy ...