A survey of techniques for architecting DRAM caches

Conference/Journal
IEEE
Authors
Sparsh Mittal Jeffrey S Vetter
BibTex
Abstract
Abstract: Recent trends of increasing core-count and memory/bandwidth-wall have led to major overhauls in chip architecture. In face of increasing cache capacity demands, researchers have now explored DRAM, which was conventionally considered synonymous to main memory, for designing large last level caches. Efficient integration of DRAM caches in mainstream computing systems, however, also presents several challenges and several recent techniques have been proposed to address them. In this paper, we present a ...