Architecting SOT-RAM Based GPU Register File

Conference/Journal
IEEE
Authors
Sparsh Mittal Rajendra Bishnoi Fabian Oboril Haonan Wang Mehdi Tahoori Adwait Jog Jeffrey S Vetter
BibTex
Abstract
With increase in GPU register file (RF) size, its power consumption has also increased. Since RF exists at the highest level in cache hierarchy, designing it with memories with high write latency/energy (eg, spin transfer torque RAM) can lead to large energy loss. In this paper, we present an spin orbit torque RAM (SOT-RAM) based RF design which provides higher energy efficiency than SRAM and STT-RAM RFs while maintaining performance same as that of SRAM RF. To further improve energy efficiency of SOT-RAM based RF, we ...