๐ฃ๐ฎ๐ฝ๐ฒ๐ฟ ๐๐ฐ๐ฐ๐ฒ๐ฝ๐๐ฎ๐ป๐ฐ๐ฒ ๐๐ป๐ป๐ผ๐๐ป๐ฐ๐ฒ๐บ๐ฒ๐ป๐ : SLIM: A Scalable Large Integer Multiplier with Run-time Configurable Operand Length for FPGAs has been accepted at ISVLSI 2026
Paper titled โSLIM: A Scalable Large Integer Multiplier with Run-time Configurable Operand Length for FPGAsโ has been accepted at the IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2026.
Authors: Sasi Snigdha Yadavalli, Rajesh Kedia
Authorโs Affiliation:
- Sasi Snigdha Yadavalli: IIIT Bangalore (SURE Intern 2025 at IIT Hyderabad)
- Rajesh Kedia: Dept. of CSE, IIT Hyderabad
๐ Congratulations to the authors!
๐ Key Highlight / Summary: The paper proposes a highly configurable and scalable large integer multiplier, SLIM, which multiplies slices of large operands using a smaller base multiplier.
Designed specifically for FPGAs, SLIM uniquely combines runtime configurable operand width with design-time configurable base multiplier width and interface width for streaming operands and results. Thanks to this architecture, it consumes considerably less time and FPGA resources compared to existing runtime configurable large integer multipliers.