Invited Talk by Dr.Balaji Raman:"Stochastic Models for System-Level Performance Analysis of Multimedia Embedded Systems"

Invited Talk by Dr.Balaji Raman:”Stochastic Models for System-Level Performance Analysis of Multimedia Embedded Systems”

Title: Stochastic Models for System-Level Performance Analysis of Multimedia Embedded Systems
Speaker: Dr.​Balaji Raman
Host Faculty: Dr. Ramakrishna Upadrasta
Room No: LH-221
Time: 15:00 hrs


In this talk, first, I will motivate the use of probabilistic analytical models for performance analysis of SoCs running Multimedia applications for Embedded Systems.

Second, I will present the stochastic model I developed to estimate an application parameter (the initial play-out delay) in the context of an SoC running a video decoding application. I will present the benefits of ​precisely ​estimating this initial play-out delay in terms of saving processor and memory resources. I will compare the analytical model with a model-checking technique (statistical model checking) for accuracy and speed.

Third, I will conclude the talk with my future research plans: (a) software for SoC performance analysis for Multimedia, Automotive, and other applications; and (2) statistical model checking for Mixed-Signal simulation and Ribo-Nucleic Acid folding.

Speaker’s Bio:​

Balaji Raman received his Masters (by research) degree and PhD at the School of Computing, National University of Singapore in 2004 and 2010 respectively. During his doctoral studies, he was a visiting scholar for six months at the Ecole Polytechnique Federal De Lausanne (EPFL), Lausanne, Switzerland.

His primary research area is Embedded Systems: (a) he develops and applies analytical models for system level performance analysis of System-on-Chips (SoCs) for Multimedia Applications; (b) he explored the similarities and differences between a model-checking technique and a performance analysis technique, during one of his postdoc’s at the VERIMAG laboratory near Grenoble, France.

His paper published in the International conference on Hardware/Software Co-Design and System Synthesis (CODES+ISSS) was among the top two papers nominated for the best paper award in 2006. He received the President’s graduate fellowship (from 2007 to 2008 in Singapore) in recognition of outstanding research excellence and promise. His secondary research area is Computational Biology; he studied predicting the structure of Ribo Nucleic Acids during his other postdoc at Ecole Polytechnique, Paris, France.

Until recently he worked as a Research and Development Software Engineer at Mentor Graphics in the Grenoble area, France; he developed software for Mixed-Signal circuit simulation tools. He has now relocated from France to India to pursue his passion in research and teaching in academics.

Wednesday, October 28, 2015 - 15:00